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Senior SoC RTL Design Engineer (remote)
Portland, ORSenior/Staff or Principal SoC RTL Design Engineer
Remote / work from any US location
US Citizen or US Permanent Resident
Primary Responsibilities
• Assist with silicon bring-up
• Contribute to all areas of SoC design, verification, and implementation
• Design, implement and integrate complex SoC blocks
• Develop block-level test cases to deliver fully functional designs
• Develop micro-architecture specifications based on the SoC requirements
• Develop synthesis constraints and resolve timing issues
• Identify and resolve RTL and Gate-Level Simulation (GLS) failures at block and chip level
• Participate in architectural feasibility studies
• Participate in ECO implementation
• Projects range from integrating third party IPs to designing complex systems
• Resolve Lint, CDC, and DFT related issues
Required Skills
• BSEE/MSEE with 15+ years of SoC design/architecture experience
• Clock domain crossing methodologies
• Experience with RISC-V architecture
• Logic synthesis and static timing analysis
• Modeling SoC architectures with FPGAs
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Third Party IP Integration experience
• Working knowledge of PCIe and DDR
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
• Working knowledge of SoC design with Chisel (plus)
• Asynchronous logic design (plus)
Competitive salary scaled based on experience + Bonus + Stock + Benefits (Employer paid health care, Employer contribution to health savings account, Flexible time off, Flexible work location with remote options, 401K employer match)
#SoC #RTL #RTLdesign #GLS #Lint #CDC #DFT #SoCdesign #RISCV #Chisel #GateLevelSimulation
Remote / work from any US location
US Citizen or US Permanent Resident
Primary Responsibilities
• Assist with silicon bring-up
• Contribute to all areas of SoC design, verification, and implementation
• Design, implement and integrate complex SoC blocks
• Develop block-level test cases to deliver fully functional designs
• Develop micro-architecture specifications based on the SoC requirements
• Develop synthesis constraints and resolve timing issues
• Identify and resolve RTL and Gate-Level Simulation (GLS) failures at block and chip level
• Participate in architectural feasibility studies
• Participate in ECO implementation
• Projects range from integrating third party IPs to designing complex systems
• Resolve Lint, CDC, and DFT related issues
Required Skills
• BSEE/MSEE with 15+ years of SoC design/architecture experience
• Clock domain crossing methodologies
• Experience with RISC-V architecture
• Logic synthesis and static timing analysis
• Modeling SoC architectures with FPGAs
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Third Party IP Integration experience
• Working knowledge of PCIe and DDR
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
• Working knowledge of SoC design with Chisel (plus)
• Asynchronous logic design (plus)
Competitive salary scaled based on experience + Bonus + Stock + Benefits (Employer paid health care, Employer contribution to health savings account, Flexible time off, Flexible work location with remote options, 401K employer match)
#SoC #RTL #RTLdesign #GLS #Lint #CDC #DFT #SoCdesign #RISCV #Chisel #GateLevelSimulation
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Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)