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Lead ASIC Design Verification Engineer (UVM)
Job Description:
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build UVM testbenches for our current programs while simultaneously defining the verification methodology, infrastructure, and hiring plan that will scale the function from a single contributor to a full team. You will be the technical authority on verification – setting coverage-driven sign-off criteria, owning verification schedule and risk for tapeouts, and making the build-versus-buy calls on VIP, tools, and compute. If you have been the strongest verification engineer on someone else’s team and want to build your own, this is the role.
Key Responsibilities and Qualifications:
Technical Leadership
• Define and own the ASIC verification methodology, standards, and sign-off criteria across company programs.
• Architect UVM-based verification environments for digital SoCs, memory subsystems, secure boot and cryptographic subsystems, and die-to-die interfaces.
• Establish reusable verification infrastructure — base classes, VIP strategy, scoreboarding and checker architecture, register abstraction (UVM RAL), and coverage models — designed for reuse across programs and derivative parts.
• Own verification planning: testplan development, coverage closure strategy, regression architecture, and quantitative sign-off metrics reported to program and customer stakeholders.
• Serve as the verification voice in design and architecture reviews, and as the technical interface to customers, primes, and government stakeholders on verification approach and evidence.
Team Building
• Onboard, mentor, and technically develop verification engineers, including junior engineers and design engineers transitioning into verification.
• Define team structure, roles, and hiring profiles for the verification organization; participate directly in recruiting, interviewing, and selection.
• Establish and enforce code review, revision control, documentation, and traceability practices appropriate to defense-qualified deliverables.
• Allocate verification effort across concurrent programs and communicate resourcing risk to engineering and program management.
Hands-On Execution
• Write SystemVerilog/UVM testbench code, sequences, agents, and functional coverage models — this role is expected to remain approximately 50–70% hands-on.
• Drive constrained-random and directed verification to coverage closure; triage failures and drive root-cause resolution with designers.
• Apply complementary methods where they are the right tool: formal property verification, assertion-based verification (SVA), gate-level simulation, and emulation/prototyping.
• Support verification of radiation-hardening and fault-tolerance features, including TMR structures, error detection and correction, and SEU/SET mitigation behavior.
• Support post-silicon bring-up by correlating silicon behavior to pre-silicon models and closing verification gaps.
• Own and maintain regression infrastructure, simulation licensing and compute utilization, and CI for verification.
Required Qualifications:
• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of ASIC/SoC verification experience, with demonstrated ownership of verification for at least one production tapeout.
• Expert-level SystemVerilog and UVM. You have architected UVM environments from scratch — not only extended environments built by others.
• Strong command of constrained-random verification, functional coverage, coverage-driven closure, and assertion-based verification with SVA.
• Experience with commercial simulation and coverage tools (Synopsys VCS/Verdi, Cadence Xcelium, and/or Siemens Questa) and with regression management at scale.
• Working knowledge of digital design and RTL — sufficient to read, reason about, and debug a designer's code, and to argue productively about intent versus implementation.
• Scripting proficiency for verification infrastructure (Python, Perl, TCL, and shell) and fluency with Git-based workflows and Linux development environments.
• Demonstrated technical leadership: mentoring engineers, leading a verification effort, or owning verification schedule and sign-off for a program.
• Clear written and verbal communication — including the ability to present verification status and evidence to non-verification stakeholders and customers.
• U.S. Citizenship is required due to ITAR and DFARS requirements applicable to our programs, along with the ability to obtain and maintain a U.S. Government security clearance.
Job Description:
A Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build UVM testbenches for our current programs while simultaneously defining the verification methodology, infrastructure, and hiring plan that will scale the function from a single contributor to a full team. You will be the technical authority on verification – setting coverage-driven sign-off criteria, owning verification schedule and risk for tapeouts, and making the build-versus-buy calls on VIP, tools, and compute. If you have been the strongest verification engineer on someone else’s team and want to build your own, this is the role.
Key Responsibilities and Qualifications:
Technical Leadership
• Define and own the ASIC verification methodology, standards, and sign-off criteria across company programs.
• Architect UVM-based verification environments for digital SoCs, memory subsystems, secure boot and cryptographic subsystems, and die-to-die interfaces.
• Establish reusable verification infrastructure — base classes, VIP strategy, scoreboarding and checker architecture, register abstraction (UVM RAL), and coverage models — designed for reuse across programs and derivative parts.
• Own verification planning: testplan development, coverage closure strategy, regression architecture, and quantitative sign-off metrics reported to program and customer stakeholders.
• Serve as the verification voice in design and architecture reviews, and as the technical interface to customers, primes, and government stakeholders on verification approach and evidence.
Team Building
• Onboard, mentor, and technically develop verification engineers, including junior engineers and design engineers transitioning into verification.
• Define team structure, roles, and hiring profiles for the verification organization; participate directly in recruiting, interviewing, and selection.
• Establish and enforce code review, revision control, documentation, and traceability practices appropriate to defense-qualified deliverables.
• Allocate verification effort across concurrent programs and communicate resourcing risk to engineering and program management.
Hands-On Execution
• Write SystemVerilog/UVM testbench code, sequences, agents, and functional coverage models — this role is expected to remain approximately 50–70% hands-on.
• Drive constrained-random and directed verification to coverage closure; triage failures and drive root-cause resolution with designers.
• Apply complementary methods where they are the right tool: formal property verification, assertion-based verification (SVA), gate-level simulation, and emulation/prototyping.
• Support verification of radiation-hardening and fault-tolerance features, including TMR structures, error detection and correction, and SEU/SET mitigation behavior.
• Support post-silicon bring-up by correlating silicon behavior to pre-silicon models and closing verification gaps.
• Own and maintain regression infrastructure, simulation licensing and compute utilization, and CI for verification.
Required Qualifications:
• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of ASIC/SoC verification experience, with demonstrated ownership of verification for at least one production tapeout.
• Expert-level SystemVerilog and UVM. You have architected UVM environments from scratch — not only extended environments built by others.
• Strong command of constrained-random verification, functional coverage, coverage-driven closure, and assertion-based verification with SVA.
• Experience with commercial simulation and coverage tools (Synopsys VCS/Verdi, Cadence Xcelium, and/or Siemens Questa) and with regression management at scale.
• Working knowledge of digital design and RTL — sufficient to read, reason about, and debug a designer's code, and to argue productively about intent versus implementation.
• Scripting proficiency for verification infrastructure (Python, Perl, TCL, and shell) and fluency with Git-based workflows and Linux development environments.
• Demonstrated technical leadership: mentoring engineers, leading a verification effort, or owning verification schedule and sign-off for a program.
• Clear written and verbal communication — including the ability to present verification status and evidence to non-verification stakeholders and customers.
• U.S. Citizenship is required due to ITAR and DFARS requirements applicable to our programs, along with the ability to obtain and maintain a U.S. Government security clearance.